1. Field of the Invention
The present invention relates to a transistor having a lightly-doped-drain (hereinafter abbreviated as LDD) for use in integrated circuits such as liquid crystal devices and image sensors. The invention also relates to a manufacture method of the transistor.
2. Description of the Related Art
With an increasing degree of IC integration, the gate length of insulated gate transistors represented by MOS transistors has become shorter year by year and is now on the order of sub-microns.
Such a reduction in the gate length makes the gradient of an electric field at the drain edge so steep as to generate hot electrons. The generation of hot electrons deteriorates characteristics of MOS transistors. An LDD structure is proposed to solve the above problem. The LDD structure intends to reduce the impurity concentration at the drain edge to moderate the electric field at the drain edge, thereby preventing deterioration in characteristics of MOS transistors.
A conventional manufacture method of an LDD-MOS transistor will be described below with reference to FIGS. 26 to 30.
(1) After forming isolating regions 2 on a P-type semiconductor substrate 1, a gate oxide film 3 is formed 100 to 200 angstroms on an active region (FIG. 26).
(2) After forming a polycrystalline silicon on the substrate surface, an impurity is doped in the polycrystalline silicon film and is patterned by photolithography to form a gate electrode 4. Phosphorus, for example, is then doped in dose amount of 5E12 to 1E14 atoms/cm.sup.2 (5.times.10.sup.12 to 1.times.10.sup.14 atoms/cm.sup.2) by ion implantation to form regions 8, 8' with the oxide films of the isolating regions 2 and the polycrystalline silicon of the gate electrode 4 used as a mask (FIG. 27).
(3) A SiO.sub.2 film 9 is formed 2000 to 4000 angstroms on the substrate surface by the CVD process (FIG. 28).
(4) Side spacers 10, 10' are formed by etch-back on both sides of the polycrystalline silicon gate electrode 4 (FIG. 29).
(5) Arsenic (As), for example, is doped in dose amount of 5.times.10.sup.15 to 1.times.10.sup.16 atoms/cm.sup.2 by ion implantation with the oxide films of the isolating regions 2, the polycrystalline silicon of the gate electrode 4 and the side spacers 10, 10' used as a mask. Then, the ion-implanted impurity is activated by heat treatment to form drain/source regions 11, 11' (FIG. 30). At this time, parts of the regions 8, 8' are left as drain/source regions 12, 12'.
An nMOS transistor of the LDD structure is fabricated through the manufacture process explained above In the transistor of FIG. 30, the drain 12 is formed with lower impurity concentration than the drain 11. As a result, an electric field at the drain end is moderated.
However, the above prior art has the following problem. Due to variations in the size of the side spacers 10, 10' formed by etch-back of the SiO.sub.2 film deposited using the CVD process, the region of the lightly-doped drain 12 is also varied in size. Such a change in the length of the lightly-doped region varies transconductance (gm) of the MOS transistor and hence impedes achievement of stable MOS characteristics.
It has been difficult to precisely control the size of the side spacers 10, 10' for the reason below. Generally, a thickness of the SiO.sub.2 film 9 is varied about 5 to 10 % in the wafer plane. Then, the size of the side spacers 10, 10' is determined depending on the thickness of the SiO.sub.2 film 9. Accordingly, variations in the thickness of the SiO.sub.2 film 9 directly affect variations in the size of the side spacers 10, 10'.